m02050 can support either a 3.3v or 3.3v/5v supply the m02050 is an integrated high-gain limiting amplifier. featuring pecl outputs, the m02050 is usable in applica- tions up to 2.5 gbps. full output swing is achieved even at minimum input sensitivity. the m02050 operates with a 3.3v or 3.3v/5v supply. rate select is supported for sfp applications and/or to achie ve optimum sensitivity at data rates 1.25 gbps. when rate select is high, optimum sensitivity is achieved at 2.5 gbps. the m02050 also includes two analog rssi outputs propor- tional to either the average or peak-to-peak input signal and a programmable signal-level detector allowing the user to set thresholds at which the logic output s are enabled. the m02050 is pin compatible with the m02040 2.1 gbps post amplifier. i i n n p p u u t t s s the data inputs are internally connected to v t t via 50 w resist ors, and generally need to be ac coupled. the nominal v tt voltage is 2.85v because of the internal resistor divider to v c c , which means this is the dc potential on the data input s. see the applications information section for further details on choosing the ac-coupling capacitor. d d c c o o f f f f s s e e t t c c o o m m p p e e n n s s a a t t i i o o n n m02050 contains an internal dc autozero circuit that can remove the effect of dc offsets without using external component s . this circuit is configured such that the feed- back is effective only at frequencies well below the lowest frequency of interest. the low frequency cut off is typically 25 khz. p p e e c c l l o o u u t t p p u u t t s s the m02050 f eatures 100k/300k pecl compliant output s. the outputs may be terminated using any standard ac or dc-coupling pecl termination technique. ac-coupling is used in applications where the average dc cont ent of the data is zero e.g. sonet. the advantage of this approach is lower power consumption, no susceptibility to dc drive and compatibility with non-pecl int erfaces. l l o o s s s s o o f f s s i i g g n n a a l l ( ( l l o o s s ) ) the m02050 f eatures input signal le vel detection over an extended range. using an external resistor, rst, between pin st set and v cc , the user can program the input signal threshold. the l os signal is active when the signal is below the threshold value. the signal detection circuitry has the equivalent of 3.5 db (typical) electrical hysteresis. rst establishes a threshold voltage at the st set pin. internally, > > 4 mv maximum input sensi- tivity at 2.5 gbps > > pecl outputs > > rate selection for 1.25 gbps > > average and peak-to-peak receive power monitor outputs > > low power (< 180 mw) > > 16 pin 3x3 qfn, standard/green package > > k k e e y y f f e e a a t t u u r r e e s s limiting amplifier for applications up to 2.5 gbps m02050
w w w w w w . . m m i i n n d d s s p p e e e e d d . . c c o o m m / / s s a a l l e e s s o o f f f f i i c c e e s s general inf ormation: (949) 579-3000 headquarters C newport beach 4000 macarthur blvd., east tower newport beach, ca 92660-3007 02050-BRF-001-A ?2005 mindspeed technologies, inc. all rights reserved. mindspeed and the mindspeed logo ar e trademarks of mindspeed technologies. all other trademarks are the property of their respective owners. although mindspeed technologies strives for accuracy in all its publications, this material may contain errors or omissions and is subject to change without notice . this material is pro vided as is and without any express or implied warranties, including merchantability, fitness for a particular purpose and non-infringement. mindspeed technologies shall not be liable for any special, indirect, incidental or consequential damages as a result of its use. a a p p p p l l i i c c a a t t i i o o n n s s ? 2.5 gbps stm-16/oc-48 sdh/sonet ?1.06, 2.12 gbps fibre channel ?1.25 gbps ethernet ?2.67 gbps sdh/sonet with fec f f e e a a t t u u r r e e s s ?operates with a 3.3v (-4 or 3.3v/5v (-5?supply ?4 mv maximum input sensitivity at 2.5 gbps ?cml outputs ?rate selection for 1.25 gbps oper ation ?average receive power monitor output (rs si a vg ) o o r r d d e e r r i i n n g g i i n n f f o o r r m m a a t t i i o o n n ?m02050--4 3.3v supply ?m02050--5 3.3v /5.5v supply p p r r o o d d u u c c t t h h i i g g h h l l i i g g h h t t s s the input signal level is monitored by the level detector (which also outputs the rssi pp voltage). as described in the rssi pp s ection, this voltage is proportional to the input signal peak t o peak value. the voltage at st set i s internally compared to the signal le v el from the level detector. when the level detector voltage is less than v(st set ), los is asserted and will stay asserted until the input signal level increases by a p redefined amount of hysteresis. when the input level increases by more than this hysteresis above v(st set ), los is de-asserted. p p e e a a k k - - t t o o - - p p e e a a k k r r e e c c e e i i v v e e d d s s t t r r e e n n g g t t h h i i n n d d i i c c a a t t o o r r ( ( r r s s s s i i p p p p ) ) the rssi pp output voltage is logarithmically proportional to the peak-to-peak level of the input signal. it is not necessary t o connect an external capacitor to this output. internally, the rssi voltage is compared with a user selectable reference to determine loss of signal as described in the previous section. j j a a m m f f u u n n c c t t i i o o n n when asserted, the active high power down (jam) pin forces t he outputs to a logic ne state. this ensures that no data i s propagated through the system. the loss of signal detec- tion circuit can be used to automatically force the data outputs to a high state when the input signal falls below the threshold. the function is normally used to allow data to p ropagat e only when the signal is above the user's bit-error- rate requirement. it, therefore, inhibits the data outputs toggling due to noise when there is no signal present (quelch? in order to implement this function, los should be connected to the jam pin, thus forcing the data outputs to a logic ne state when the signal falls below the threshold. a a v v e e r r a a g g e e d d r r e e c c e e i i v v e e d d s s t t r r e e n n g g t t h h i i n n d d i i c c a a t t o o r r ( ( r r s s s s i i a a v v g g ) ) the rssi a vg output current is a mirrored version of the rxavg in current from compatible tias. it sources rather than sinks the current making it compatible with ddmi type inter- faces. m02050 block diagram biasing jam ref r ate sel output buf fer of fset can cel comparator v cc los rssi pp pecln peclp st set dinp dinn rx avg in rssi avg level detector threshold setting circuit level shift v tt limiting amplifier
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